Modern integrated circuits (ICs), which may also be referred to as “chips”, are made up of alternating conducting layers and insulating layers which are formed over a semiconductor substrate. The alternating conducting and insulating layers collectively establish electrical connection to active regions of devices in the semiconductor substrate (e.g., source/drain regions of a MOSFET or emitter/base/collector regions of a BJT in the substrate). Exterior pins or pads, which are often electrically connected to an upper conducting layer, allow the semiconductor devices to send and receive signals to and from exterior electrical components, such as other circuits or audio/visual input/outputs, for example.
In many cases, the conducting and insulating layers over different types of devices can have different topographies. For example, at some stages during manufacture, a single IC can include low-voltage logic devices having one topography (e.g., a polysilicon layer exhibiting short sidewalls having a low aspect ratio) as well as FinFETS and/or flash memory devices that have other topographies (e.g., a polysilicon layer exhibiting tall, steep sidewalls having a high aspect ratio). Although the use of these different topographies allows integration of several different types of devices onto a single integrated circuit, the variation in aspect ratio and/or height (e.g., relative to a top surface of the substrate) for these different types of devices can lead to challenges in the manufacturing process.
To help streamline the manufacturing process of such devices on a single integrated circuit, this disclosure provides improved manufacturing processes.